The field of invention relates to the testing of semiconductor chips; and more specifically, to a method and apparatus for distributed test pattern decompression.
FIG. 1 relates to a traditional method for downloading test patterns from a storage resource 105 (e.g., a server, a mainframe, a magnetic disk array, a magnetic tape drive, etc.) to a semiconductor chip tester 102. Test patterns, when fully downloaded, are eventually applied to a semiconductor chip which is also referred to as a Device Under Test (DUT). The DUT typically has a plurality of input, output, or input/output connections 101a through 101d (e.g, pins, balls, leads, etc.) that receive applied test signals and/or provide responses to the applied test signals. The tester 102 then observes the response of the semiconductor chip to these applied test signals.
By comparing the observed responses against allowable or expected signals, proper functional operation of the semiconductor chip can be verified. The test controller 107 is a portion of the tester 102 that controls the application of one or more test signals to a semiconductor chip.
Each of the DUT connections 101a through 101d may correspond to a single semiconductor chip input connection, or a group of semiconductor chip input connections, depending upon the architecture of the test controller 107. The test controller also has one or more testing interfaces 130a through 130d (e.g., a flex cable) for sending the test patterns to the semiconductor chip. The test controller 107 may also be designed to observe one or more output signals generated by the semiconductor chip in response to the applied test patterns.
In development and/or manufacturing environments, the digital information used to generate a test signal that is applied to a DUT connection (or the digital information that corresponds to the expected data received from a DUT connection in response to a test signal) is typically stored in storage resource 105. The information described just above, may be referred to as test pattern data.
Test pattern data may take various forms. For example, in one embodiment, the digital information is a xe2x80x9ctest vectorxe2x80x9d that corresponds to the digital information to be received by a DUT connection during test. In a related embodiment, the digital information is a xe2x80x9cresponse vectorxe2x80x9d that corresponds to the expected data to be transmitted by a DUT connection during test. Typically, although not a strict requirement, the test pattern data (which may also be referred to a test pattern, test pattern information, and the like), is organized at the DUT connection level. That is, a discrete test pattern is identified as corresponding to a particular DUT connection on a semiconductor chip.
Because a large amount of test pattern data may be used to test a semiconductor chip, the test pattern data is typically stored in a compressed format within the storage resource 105. The compressed test patterns are typically sent from the storage resource 105 to a central processing unit (CPU) 103 (typically over a network 104 such as a local area network (LAN)).
The CPU 103 is communicatively coupled to the tester 102 (e.g., via an industry standard interface (e.g., a PCI bus) or a proprietary interface) or designed as an integral part of the tester 102. The CPU 103 typically comprises a processor that runs software and may be implemented by various means such as a personal computer or workstation that stands outside the tester 102. In other instances the CPU 103 may be implemented on a xe2x80x9cmotherboardxe2x80x9d (e.g., having one or more processor chips) that resides within the same mechanical package as the tester 102.
The CPU 103 may be designed to take on various responsibilities such as: 1) acting as a gateway between the network 104 and the tester 102; 2) performing the aforementioned comparison of observed test signals (that are responsive to the applied test patterns) against their expected or allowable values to assess proper/improper functionality of the semiconductor chip; and/or 3) performing the needed decompression on the test pattern data that is received from the network 104 before it is stored into memory 108.
That is, after compressed test pattern data is received from the network 104 at the CPU 103, the CPU decompresses this data before it is forwarded to the tester 102 and stored in memory 108. A decompression algorithm performed by the CPU 103 effectively extracts the test pattern data to its original form (i.e., as it existed prior to being compressed for storage into storage resource 105). The decompression algorithm may be executed: 1) via a software program that is executed by the processor(s) within the CPU 103; and/or 2) within one or more separate semiconductor chips designed to perform the decompression algorithm in logic. The term decompression engine 106 may be used to refer to these approaches as well as others should they exist.
The tester 102, in various embodiments, may often be viewed as having a parallel arrangement of test controllers and memory devices. That is, the basic test controller 107 and memory 108 architecture may be viewed as being repeated so that a sufficient number of testing interfaces 130a through 130d are created to properly test the semiconductor chip. In order to partially expand the number of DUT testing interfaces, multiple test controllers may be controlled/monitored and/or accessed through a single point of reference such as controller 111 and its corresponding interfaces 112a, 112b, etc.
A plurality of such reference points may be coupled to a central bus 110 to fully expand the number or testing interfaces offered by the tester 102. A CPU interface 109 may also be coupled to the central bus 110 to enable the sending of decompressed test data patterns through the tester 102 and into their proper memory locations. Once the decompressed data patterns are stored in their proper memory unit (such as memory unit 108 for test patterns used with DUT connections 101a through 101d), the test controller 107 that is coupled to the memory unit 108 extracts the decompressed data patterns and applies them to the appropriate DUT connections 101a through 101d in accordance with the overall testing scheme designed for the semiconductor chip being tested.
As semiconductor chip manufacturing techniques continue to advance, however, semiconductor chips are becoming more and more sophisticated. For example, over time, the number of DUT connections on a typical semiconductor chip as well as the performance level of a typical semiconductor chip has continued to expand. With the continued increase in DUT connections and functional performance, the ability to test a semiconductor chip becomes increasingly difficult.
Specifically, with the increase in functional performance, more lengthy and sophisticated test signals are applied or observed at a semiconductor chip""s DUT connections. Furthermore, as the number of discrete DUT connections are increasing, the number of test pattern files to be applied to a semiconductor chip are increasing in response. The result of these trends is that the total amount of test pattern data to be applied to a particular semiconductor chip during testing is growing at a rapid rate.
That is, for example, the amount of the storage 105 space that is consumed by a chip""s test patterns is expanding at a high rate. As a result, the traditional test pattern loading sequence described just above has become too time consuming. For example, currently, it may take as long as 2 hours for all of a semiconductor chip""s test pattern data to be decompressed and loaded from storage space 105 into its proper memory device locations.